This application claims the benefit of Japanese application No. 2001-001169, filed Jan. 9, 2001, the disclosure of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a power semiconductor module, typically utilized in a power conversion apparatus, such as an inverter or power supply, and more particularly the present invention relates to a power semiconductor device, such as an insulated-gate bipolar transistor or an intelligent power module, which incorporates a drive circuit in the same package.
2. Description of the Related Art
FIG. 6 is a block diagram showing an inverter for a pulse width modulation (xe2x80x9cPWMxe2x80x9d hereinafter) control apparatus, using an intelligent power module (xe2x80x9cIPMxe2x80x9d hereinafter).
In FIG. 6, IPM 30 includes a high voltage IC (integrated circuit) (hereinafter referred to as an HVIC) 31, which is inputted with U-phase, V-phase, and W-phase PWM signals PWMU, PWMV, PWMW, and a PWMOFF signal, and generates driving signals for brake element 36 and inverter element 35, which converts direct current (DC) power to alternating current (AC) power by using the above-mentioned driving signals to cause power semiconductor devices to perform switching.
Furthermore, IPM 30 is also provided with protective circuits for performing such functions as overcurrent protection, short-circuit protection, overheat protection, supply under-voltage protection, and accident diagnostic circuits for outputting a warning to the outside when a protective circuit operates. However, for the sake of expediency, these circuits have been omitted from FIG. 6.
HVIC 31, as will be described in detail below, includes: a signal generating circuit 32, which is inputted with PWM signals PWMU, PWMV, PWMW, and a PWMOFF signal, and generates six PWM signals; a level shifting circuit 33 for converting the level of PWM signals for each insulated-gate bipolar transistor (hereinafter referred to as IGBT) of the three upper arms of inverter element 35, for example, to signals that use a positive direct current potential as a reference; and a driving circuit 34 for generating and outputting driving signals (ON, OFF signals) at levels capable of driving each IGBT, based on the total of six PWM signals from the signal generating circuit 32 and level shifting circuit 33.
Inverter element 35 includes a pair of switching arms 351 and 352, each including an IGBT and a free wheeling diode connected in an inverse-parallel condition thereto, and connected in series top and bottom. The three-phase (U-phase, V-phase, W-phase) segments of inverter element 35 are connected in parallel, but for the sake of expediency, only the U-phase segment is shown in the example given in FIG. 6.
Further, brake element 36 generates a damping force for applying a brake to a three-phase AC motor 80, which is the load of inverter element 35.
FIG. 6 also illustrates an AC power supply 70, a converter 60 for performing AC/DC conversion, and a smoothing capacitor C, with terminals of the smoothing capacitor C being connected to the DC terminals P, N of inverter element 35.
Further, three-phase AC motor 80 may be connected to output terminals U, V, W of each phase of the inverter element 35.
Furthermore, the above-mentioned PWM signals PWMU, PWMV, PWMW and PWMOFF signal, and a brake input signal are inputted to HVIC 31 inside IPM 30 from a CPU 40 via an upstream-downstream insulating circuit 50 such as a photocoupler, with reference numeral 90 designating the power supply for IPM 30, CPU 40 and insulating circuit 50.
FIG. 7 shows the above-mentioned signal generating circuit 32 in more detail. Signal generating circuit 32 includes: inverting circuit 321 to which a PWMOFF signal is inputted; inverting circuits 322U, 322V, 322W to which PWM signals PWMU, PWMV, PWMW are respectively inputted; dead-time generating circuits 323U, 323V, 323W to which PWM signals PWMU, PWMV, PWMW and output signals of inverting circuits 322U, 322V, 322W are respectively inputted; and AND circuits 324U, 324V, 324W, 325U, 325V, 325W, which are inputted with respective output signals from dead-time generating circuits 323U, 323V, 323W and an output signal from inverting circuit 321, and which output PWM signals to the IGBT of the upper and lower arms of each phase.
Regarding signal generating circuit 32, the output signal of AND circuit 324U makes up PWM signal PWMU for the IGBT of the upper arm of the U-phase, the output signal of AND circuit 325U makes up PWM signal PWMX for the IGBT of the lower arm of the U-phase, the output signal of AND circuit 324V makes up PWM signal PWMV for the IGBT of the upper arm of the V-phase, the output signal of AND circuit 325V makes up PWM signal PWMY for the IGBT of the lower arm of the V-phase, the output signal of AND circuit 324W makes up PWM signal PWMW for the IGBT of the upper arm of the W-phase, and the output signal of AND circuit 325W makes up PWM signal PWMZ for the IGBT of the lower arm of the W-phase.
In signal generating circuit 32 of FIG. 7, for example, PWM signal PWMU and a signal that inverts the phase thereof 180xc2x0 are inputted to U-phase dead-time generating circuit 323U. Then, to prevent a short circuit due to simultaneously turning ON the IGBT of the upper and lower arms, dead time is created and outputted between the two input signals.
When the PWMOFF signal is not inputted (when the PWMOFF signal is at a xe2x80x9clowxe2x80x9d level), the output signals of dead-time generating circuit 323U outputted via AND circuits 324U and 325U makes up, respectively, PWM signals PWMU and PWMX for the IGBT of the U-phase upper and lower arms as-is. Further, when the PWMOFF signal is inputted (when the PWMOFF signal is at a xe2x80x9chighxe2x80x9d level), there are no output signals from AND circuits 324U and 325U, and PWM signals PWMU, PWMX are OFF.
In addition, xe2x80x9cLoad Current Polarity Discrimination Method and Inverter Systemxe2x80x9d disclosed in Japanese patent application laid-open publication no. 7-7967 (Jan. 10, 1995), discloses an attempt to compensate for dead time by determining the polarity of the motor current and correcting the PWM signal. This is because an error occurs between the inverter voltage that originally should have been outputted and the actual inverter output voltage due to the effect of dead time, and this error voltage distorts the motor current.
Thus, Japanese patent application laid-open publication no. 7-7967 relates to a dead-time compensation method for an inverter apparatus for converting DC to AC and supplying this AC to a load by using PWM signals to alternately turn upper and lower arm switching devices ON and OFF while interposing dead time that turns the upper and lower arm switching devices OFF simultaneously. Japanese patent application laid-open publication no. 7-7967 is directed to an inverter dead-time compensation method for detecting the existence of current flowing through the switching device of either the upper or lower arm, for determining the instantaneous polarity of a load current from the relationship between a specific current conducting direction and the existence of current in the pertinent switching device during the interval when this switching device is in the ON state, and, in accordance with this instantaneous polarity, increasing by a predetermined correction quantity the ON interval of a PWM signal for the arm of the one side from among the PWM signals outputted to the upper arm and lower arm, and, in addition, decreasing the PWM signal ON interval by the above-mentioned correction quantity for the arm of the other side.
In Japanese patent application laid-open publication no. 7-7967, an inverter apparatus for converting DC to AC and supplying this AC to load, includes a switching device, which is connected to a DC power source in the form of upper and lower arms, and which alternately turns ON and OFF, PWM signal generating means, and a driving circuit for driving the switching device in accordance with a PWM signal. The inverter apparatus further includes: means for detecting the existence of a current flowing through the switching device of either the upper or lower arm; current direction detecting means, which is connected to PWM signal generating means and current detecting means, and which determines the instantaneous polarity of a load current by the relationship between a specific current conducting direction and the existence of current in a switching device during the interval when the switching device is in the ON state; and means for outputting either a voltage command to PWM signal generating means or a signal for correcting a PWM waveform, in accordance with the polarity of the load current.
Furthermore, xe2x80x9cTurn-ON Locking Circuit of a Transistor Switching Apparatusxe2x80x9d disclosed in Japanese patent no. 2560728 is related to a circuit for locking the turn-ON of a transistor so as to hold the dead time of a switching operation to the minimum while preventing a transistor arm short circuit.
Japanese patent no. 2560728 is sets forth the provision of turn-ON locking means, which, when the transistor of the one side corresponding to the same arm turns OFF, determines that a reverse bias voltage has been established between the base and emitter thereof, and applies a turn-ON signal to the transistor of the other side.
In the power conversion apparatuses shown in FIGS. 6 and 7, IGBT switching characteristics must be known beforehand when setting dead time via dead-time generating circuits 323U, 323V, and 323W.
For example, after providing an OFF command to the IGBT of the lower arm, to determine the delay time until an ON command is provided to the IGBT of the upper arm, consideration is given to the maximum time toff(max) after providing an OFF command to the lower arm IGBT until the collector current thereof is practically zero and to the minimum time ton(min) after providing an ON command to the upper arm IGBT until the collector current thereof begins to flow ton(min), and sufficient time is calculated for preventing a short circuit due to simultaneously turning ON the IGBT of the upper and lower arms. Each of the above-mentioned times toff(max) and ton(min) is generally measured using an existing standardized driving circuit.
However, when using another IGBT for the purpose of improving characteristics, such as reducing switching loss, a problem arises in which switching characteristics are checked, and dead time is reset each time such an IGBT is used. Further, the switching time of IGBT and other such power semiconductor devices is largely dependent on the driving circuit and the driving mode, as well as the characteristics of the device itself. In other words, because the switching characteristics of a power semiconductor device are first determined in a state wherein a driving circuit used as an IPM and a power semiconductor device are combined, the need also arises to reset dead time at the point in time when the IPM circuit is actually formed.
Furthermore, in the past, dead time was set a little longer to allow sufficient time, but this was also a problem in that, by doing so, actual output voltage and current distortion became prominent, causing inverter control performance to take a turn for the worse.
Further, the power conversion apparatus shown in Japanese laid-open patent publication no. 7-7967 was strictly directed to compensating dead time, and did not provide a technology for performing switching by automatically setting the optimum dead time.
Furthermore, in Japanese laid-open patent publication no. 7-7967, current direction detecting means for determining the polarity of the motor current (load current), and correction signal outputting means for outputting, in accordance with current polarity, either a voltage command to PWM signal generating means, or a signal for correcting a PWM command are essential. These current direction detecting means and correction signal outputting means contributed to making the circuitry more complex.
Turn-ON locking means discussed in Japanese patent no. 2560728 included a comparator for comparing a reverse bias voltage between the base and emitter of the transistor of the one side against a reference value, and a NAND gate, which is directly inputted with the outputted signal thereof, and which generates a turn-ON signal for the transistor of the opposing arm side.
However, because the reference potential differs for the upper arm transistor and lower arm transistor, normal operation cannot be maintained without the intervention of an isolating amplifier or an optoisolator between the output side of the comparator and a transistor, raising a problem from the standpoint of achieving practicability.
To solve the above and other aspects, it is an object or the present invention to provide a power semiconductor module capable of automatically setting the optimum dead time without being effected by a driving circuit, a driving mode, or the characteristics of individual power semiconductor devices.
Another object of the present invention is to provide a power semiconductor module having an enhanced control performance of the inverter so as not to set a dead time that is longer than necessary.
Further, another object of the present invention is to provide a power semiconductor module which is capable of setting the optimum dead time using a relatively simple circuit constitution.
Objects of the present invention are achieved with a semiconductor module including an inverter, for example, and a pair of power semiconductor devices, such as IGBT, disposed in upper and lower arms, respectively, and driving circuits for driving the semiconductor devices thereof.
Embodiments of the present invention are characterized in having a zero current detecting unit and a driving signal generating unit. The zero current detecting unit detects that the output current of the power semiconductor device of the arm of the one side of the upper and lower arms has practically reached zero, and driving signal generation unit generates an actual driving signal for the power semiconductor device of the arm of the other side when there exists an output signal of the zero current detecting unit (a signal, which detected that the current has almost reached zero), and there exists an ON command for the power semiconductor device of the arm of the other side.
Embodiments of the present invention including the zero current detecting unit can include the following various modes.
For example, zero current detecting unit provides current detecting circuits, such as a current transformer and shunt resistor, to the output side of a power semiconductor device, for directly detecting the output current of a power semiconductor device, and for detecting that the value thereof has become practically zero. Further, as another example, the zero current detecting may detect a current proportional to an output current, from a terminal such as a sense emitter disposed in a power semiconductor device.
Furthermore, embodiments of the present invention may also have a zero current detecting unit to detect output current from the control terminal voltage of a power semiconductor device (in the case of an IGBT, this is the voltage between the gate and the emitter).
As another example, the zero current detecting unit, in embodiments of the present invention may also provide inductance through which the output current of a power semiconductor device flows, and detect that output current is practically zero, based on current changes in this inductance.
Embodiments of the present invention preferably include a zero current detecting unit and driving signal generating unit via high-voltage ICs (HVIC). Here, driving signal generating unit includes primarily logic circuits, such as AND circuits and inverting circuits.
Further, embodiments of the present invention may be, for example, utilized as a semiconductor module for a PWM inverter, and an ON command, which is inputted to the above-mentioned driving signal generating unit in this case, including a PWM signal generated by comparing an output voltage command against a modulated wave of the inverter.
These together with other aspects and advantages which will be subsequently apparent, reside in the details of construction and operation as more fully hereinafter described and claimed, reference being had to the accompanying drawings forming a part hereof, wherein like numerals refer to like parts throughout.